1. Technical Field
A semiconductor test apparatus is disclosed that takes failure data obtained as the test results for memory cells and their corresponding addresses in memory provided in a device under test (hereinafter, DUT), sorts the failure data, and causes the data to be stored in acquisition memory by means of burst access. More particularly, a semiconductor test apparatus is disclosed that is able to write failure data to acquisition memory using burst access, even in cases when the number of addresses and failure data does not match the burst length or when irrelevant data is mixed in with the failure data, and wherein the number of memory devices constituting the acquisition memory can be reduced.
2. Description of the Related Art
In recent years semiconductor devices, particularly memory devices, have experienced dramatic increases in memory capacity, and the amount of failure data obtained as test results for memory cells and their corresponding addresses in memory is increasing.
In a semiconductor test apparatus, failure data is temporarily stored in acquisition memory, and the stored failure data is used in analysis and other processes. Typically, acquisition memory is realized by means of synchronous dynamic random access memory (SDRAM). Also, in a memory device test, the writing of failure data to acquisition memory uses SDRAM's read-modify-write operations (a series of operations wherein data that has been read out is modified, if necessary, and then written back), and thus the writing of failure data takes more time than ordinary write operations. For this reason, attempts are being made to reduce the amount of time involved in writing failure data to acquisition memory by using SDRAM's burst access functions.
In addition, acquisition memory is typically realized by means of a plurality of memory devices (such as SDRAM), and an interleaved technique is implemented to sequentially write data to this plurality of memory devices. When writing to a memory device that constitutes part of acquisition memory, the next set of failure data cannot be written to that memory device until the first write operation is finished. With the interleaved technique, failure data is written to the next memory device, without waiting for the first write operation to finish as above.
In other words, in order to continue writing failure data without a wait time, data must be written to the other memory devices by the time the memory device that was first written to becomes writeable again. For this reason, the number of memory devices increases as the write time for the memory devices constituting the acquisition memory increases.
FIG. 8 illustrates one example of a semiconductor test apparatus of the related art. The DUT 100 is a device under test. Ordinarily, in the case of a memory device test, a plurality of memory devices are tested simultaneously. The address generator 1 generates addresses corresponding to memory cells in the memory provided in the DUT 100. Ordinarily, memory cells are expressed by two-dimensional (2D) addresses (X address, Y address), and thus the address generator 1 generates 2D addresses.
The data input/output unit 2 includes: a signal generator circuit (not shown) that generates an address signal, data signal, and control signal input into the DUT 100; an output driver (not shown) that outputs a test signal to the DUT 100; a comparator (not shown) that compares the output signal from the DUT 100 to a preset comparison voltage; and a decision circuit (not shown) that compares the comparator output signal to expected value pattern data, and decides whether the information matches or does not match (pass/fail). The data input/output unit 2 outputs failure data that expresses the pass/fail obtained as a test result from the determination circuit.
The timing generator 3 generates timings for the edge of the test signal output from the driver of the data input/output unit 2 to the DUT 100, as well as timings for a signal (hereinafter referred to as the strobe signal) that determines the timings for comparing the output signal from the comparator of the data input/output unit 2 to the expected value pattern data. In addition, the timing generator 3 generates timings related to address generation and failure data collection.
The address converter 4 converts the 2D addresses generated by the address generator 1 into 1D addresses. Herein, the correspondence between an input 2D address and an output 1D address is determined in advance. The burst address converter 5 substitutes bits in the 1D address from the address converter 4 on the basis of conversion bit information set in the register 6.
During a test, if the 2D addresses generated by the address generator 1 vary discontinuously, the bits that vary are examined, and bits are substituted in the 1D address that was converted by the address converter 4. In so doing, address continuity can be kept. By varying addresses continuously, the burst access functions of SDRAM can be used. The 2D addresses generated by the address generator 1 are stated in advance in a test program by the user of the semiconductor test apparatus, and thus it is known where bits vary in the 2D addresses.
For this reason, the 1D addresses are made to vary continuously by moving the bit that varies to the lower order bits in the 1D addresses. In the conversion bit information in the register 6, information regarding the target bits to be moved to the lower order bits is set.
The sort circuit 7 takes an address from the burst address converter 5 and failure data corresponding to that address from the data input/output unit 2, resorts the data in the units required for burst access of the acquisition memory 9 (hereinafter referred to as the burst length), and outputs the result.
The memory controller 8 generates address signals, data signals, and control signals for the acquisition memory 9 on the basis of the address and failure data sorted by the sort circuit 7. The acquisition memory 9 is the device that stores the failure data. The acquisition memory 9 may be realized by means of SDRAM, for example, and includes burst access functions for continuously writing or reading data.
The operation of such a semiconductor test apparatus will now be described using FIGS. 9 and 10. FIG. 9 explains one example of a memory cell in a memory device set as a DUT. FIG. 10 explains one example of address conversion.
Herein, the case of testing a memory cell in memory like that illustrated in FIG. 9 will be described by way of example. The memory cell illustrated in FIG. 9 has m X addresses (where m is an integer equal to or greater than 0), and n Y addresses (where n is an integer equal to or greater than 0). This memory cell is tested by varying the address as indicated by the arrow in FIG. 9.
First, an operation for writing data to the memory cell of the DUT 100 is conducted. The address generator 1 generates a 2D address with X address 0, Y address 1 (hereinafter expressed simply as (0,1)). The data input/output unit 2 generates an address signal on the basis of this 2D address, and outputs the address signal to the DUT 100 together with a data signal and a control signal.
The address generator 1 then generates the 2D address (0,3). The data input/output unit 2 generates an address signal on the basis of this 2D address, and outputs the address signal to the DUT 100 together with a data signal and a control signal. This series of operations is repeated for the 2D addresses from (0,1) to (m,2).
Next, operations for reading out data from the memory cell of the DUT 100 and storing failure data in the acquisition memory 9 will be described. Similarly to the write operation, the address generator 1 generates the 2D address (0,1). The data input/output unit 2 generates an address signal on the basis of this 2D address, and outputs the address signal to the DUT 100 together with a control signal.
The data written at the address (0,3) of the DUT 100 is then output, and input into the data input/output unit 2. In the data input/output unit 2, the data that was input from the DUT 100 is compared against a comparison voltage by a comparator (not shown), and the output signal from the comparator is then compared to expected value pattern data to make a pass/fail decision. The failure data obtained as a result of this decision is output from the data input/output unit 2 to the sort circuit 7.
Meanwhile, the 2D addresses that were generated by the address generator 1 are converted by the address converter 4, the burst address converter 5, and the sort circuit 7. A specific example of this series of conversions will now be described using FIG. 10. From the address generator 1, the 2D addresses from (0,1) to (m,2) are successively generated, and input into the address converter 4.
The address converter 4 converts the 2D addresses from the address generator 1 into 1D addresses. In the example illustrated in FIG. 10, the 2D addresses are converted into 1D addresses by simply concatenating each Y address and X address from the address generator 1. In other words, the Y address is placed at the higher order bit in the 1D address, while the X address is placed at the lower order bit.
Looking at the 1D addresses, it can be seen that the 1D addresses do not vary continuously. More specifically, the first four addresses converted by the address converter 4 vary as follows: 10, 30, 00, 20. Similarly, the next four addresses vary as follows: 11, 31, 01, 21.
When viewed in groups of four addresses, it is the higher order bit of the 1D addresses that varies. In the register 6, this varying bit is set in advance as conversion bit information. On the basis of the conversion bit information in the register 6, the burst address converter 5 moves bits in the 1D addresses from the address converter 4.
In the example illustrated in FIG. 10, the burst address converter 5 moves the higher order bit to the lower order bit in the 1D addresses from the address converter 4. The sort circuit 7 then takes the 1D addresses that have been substituted by the burst address converter 5, as well as the failure data corresponding to those 1D addresses, and performs a sort such that the addresses become continuous in accordance with the burst length used during burst access of the acquisition memory 9.
In the example illustrated in FIG. 10, the burst length is taken to be 4. Consequently, the sort circuit 7 sorts and outputs four addresses and failure data as a single unit. On the basis of the 1D addresses and failure data sorted by the sort circuit 7, the memory controller 8 generates an address signal, data signal, and control signal for the acquisition memory 9. The memory controller 8 then writes the failure data to the acquisition memory 9 using burst access.
In this way, when writing failure data to the acquisition memory 9, 2D addresses generated by the address generator 1 are converted into 1D addresses by the address converter 4, and the burst address converter 5 moves bits in these 1D addresses on the basis of conversion bit information in the register 6. Subsequently, the sort circuit 7 sorts the 1D addresses and failure data such that the addresses become continuous in accordance with the burst length. In so doing, the continuity of the 1D addresses can be kept, and the failure data can be written to the acquisition memory 9 using burst access. For this reason, the time to write failure data to the acquisition memory 9 can be reduced.
Japanese Unexamined Patent Application Publication No. 2008-052770 discloses a semiconductor test apparatus that enables the test time to be reduced by improving the transfer efficiency of failure information.